1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating a semiconductor device. In particular, the present invention relates to a semiconductor device and a fabrication method thereof employing a nitride stopper method applied to memory cells such as a DRAM (Dynamic Random Access Memory) and an SRAM (Static Random Access Memory).
2. Description of the Background Art
A semiconductor device which employs the so called nitride stopper method using a nitride layer as a stopper layer has been known. FIG. 19 shows one example of a conventional semiconductor device employing the nitride stopper method.
Referring to FIG. 19, on a main surface of a silicon substrate 1, a pair of gate electrodes 2 is formed with a gate insulating layer interposed. Gate electrode 2 has, for example, a doped polysilicon layer 2a and a WSi layer 2b. 
A hard mask insulating layer 3 formed of SiO2 or the like is formed on gate electrode 2. A thin SiO2 layer 4 is formed to cover hard mask insulating layer 3 and gate electrode 2. An SiO2 sidewall spacer 15 is formed to cover side surfaces of gate electrode 2 and hard mask insulating layer 3 with the thin SiO2 covering layer 4 interposed.
An SiN stopper layer 5 is formed to cover hard mask insulating layer 3 and SiO2 sidewall spacer 15. An interlayer insulating layer 6 formed of SiO2 or the like is formed to cover SiN stopper layer 5. A contact hole 7 is formed such that contact hole 7 penetrates interlayer insulating layer 4, SiN stopper layer 5 and thin SiO2 layer 6 to reach the main surface of silicon substrate 1. Contact hole 7 is provided to reach one SiO2 sidewall spacer 15, and an SiN sidewall spacer 8a is left on the surface of the one SiO2 sidewall spacer 15.
An interconnection layer 9 is formed to extend from the inside of contact hole 7 onto interlayer insulating layer 6. Interconnection layer 9 includes a doped polysilicon layer 9a and a WSi layer 9b formed thereon.
An isolation width W4 is defined by the combines thickness of the one SiO2 sidewall spacer 15 and that of SiN sidewall spacer 8a formed on the surface of spacer 15. Insulation between gate electrode 2 and interconnection layer 9 can be obtained by setting a value of separation width W4 at a prescribed value or more. In the case of FIG. 19, for example, if a width W1 between electrodes adjacent to each other is 0.24 xcexcm, tan opening width W2 of the bottom of contact hole 7 is approximately 0.06 xcexcm.
Referring to FIGS. 20-22 next, a method of fabricating the semiconductor device shown in FIG. 19 is described. FIGS. 20-22 are cross sectional views showing the first to the third steps of a fabrication process of the semiconductor device shown in FIG. 19.
First with reference to FIG. 20, gate electrode 2 and hard mask insulating layer 3 are formed on the main surface of silicon substrate 1 with a gate insulating layer interposed, and thin SiO2 layer 4 is formed to cover these by CVD (Chemical Vapor Deposition) or the like. A silicon oxide layer is deposited on thin SiO2 layer 4 by CVD or the like, and an anisotropic etching process is applied to the silicon oxide layer. SiO2 sidewall spacer 15 is thus formed. Etching of SiO2 sidewall spacer 15 uses plasma. Therefore, plasma is applied to the main surface of silicon substrate 1.
SiN stopper layer 5 is formed to cover SiO2 sidewall spacer 15 and hard mask insulating layer 3 by the CVD or the like. Interlayer insulating layer 6 formed of SiO2 or the like is formed on SiN stopper layer 5 by CVD or the like. A resist 10 patterned into a prescribed shape is provided on interlayer insulating layer 6.
Next with reference to FIG. 21, interlayer insulating layer 6 is selectively etched using resist 10 as a mask. The etching is stopped by SiN stopper layer 5 and an opening 7a is formed.
SiN stopper layer 5 is next etched. As a result, contact hole 7 which selectively exposes the main surface of silicon substrate 1 is formed as shown in FIG. 22. An over etching process is applied to SiN stopper layer 5 so that SiN sidewall spacer 8a having a small thickness is left on the surface of SiO2 sidewall spacer 15 as shown in FIG. 22.
Interconnection layer 9 is thereafter formed to extend from the inside of contact hole 7 onto interlayer insulating layer 6 by CVD or the like. Accordingly, the semiconductor device shown in FIG. 19 is obtained through the processes described above.
Because of the plasma applied to the main surface of silicon substrate 1 exposed while SiO2 sidewall spacer 15 is formed, a problem as described below arises.
Although not shown in FIG. 19, an element isolation oxide layer is formed to surround an element formation region where an MOS transistor or the like including gate electrode 2 is formed. Stress generated when the element isolation oxide layer is formed tends to remain in the vicinity of the periphery of the element isolation oxide layer.
SiO2 sidewall spacer 15 is generally extended over the element isolation oxide layer, and a pn junction may be formed about the periphery of the element isolation oxide layer where the stress remains. In this case, the plasma is applied to the portion where the pn junction is formed. Therefore, leakage current could be easily generated at the pn junction portion. The generated leakage current deteriorates the refresh characteristic of a capacitor if the semiconductor device is a DRAM.
In addition, the opening width W2 of the bottom of contact hole 7 becomes as small as approximately 0.06 xcexcm by forming SiO2 sidewall spacer 15 as shown in FIG. 19 and as described above. As a result, the area of the opening at the bottom of contact hole 7 is decreased.
The present invention is made to solve the problems described above. An object of the invention is to provide a semiconductor device and a fabrication method thereof by which generation of leakage current resulting from the plasma applied to the main surface of the semiconductor substrate can be restricted, and the area of the opening at the bottom of the contact hole can be increased without increasing the spacing between gate electrodes.
A semiconductor device according to the present invention includes a gate electrode, a hard mask insulating layer, a thin insulating layer, a nitride stopper layer, a sidewall nitride layer, an interlayer insulating layer, and an interconnection layer. The gate electrode is formed on a main surface of a semiconductor substrate. The hard mask insulating layer is formed on a top surface of the gate electrode. The thin insulating layer is formed to cover a side surface of the gate electrode and the hard mask insulating layer. The thin insulating layer refers to an insulating layer having a thickness of approximately 5-20 nm, for example. The nitride stopper layer is directly formed on the thin insulating layer to extend from a portion on one side surface of the gate electrode onto a top surface of the hard mask insulating layer. The sidewall nitride layer is directly formed on the thin insulating layer to cover the other side surface of the gate electrode. The interlayer insulating layer is formed to cover the nitride stopper layer, and provided with a contact hole formed in a self alignment manner that reaches the main surface of the semiconductor substrate and the sidewall nitride layer. The interconnection layer is formed in the contact hole. The sidewall nitride layer may have its upper end on a side surface of the hard mask insulating layer or may cover the side surface of the hard mask insulating layer and be connected to the nitride stopper layer, provided that the sidewall nitride layer tapers away from the semiconductor substrate.
According to the semiconductor device of the present invention, the nitride stopper layer is directly formed on the thin insulating layer, and SiO2 sidewall spacer 15 is not provided between the thin insulating layer and the nitride stopper layer as in the conventional semiconductor device. Since SiO2 sidewall spacer 15 which is formed with the plasma is not provided, application of the plasma to the main surface of the silicon substrate can be avoided. As a result, generation of leakage current which is a problem of the conventional semiconductor device can be effectively minimized. Further, since SiO2 sidewall spacer 15 is not formed, the area of the opening at the bottom of the contact hole formed in the self-aligned manner between gate electrodes can be increased without increasing the spacing between gate electrodes adjacent to each other compared with the conventional semiconductor device. Since the sidewall nitride layer is provided between the gate electrode and the interconnection layer, insulation between the gate electrode and the interconnection layer can be obtained by the presence of the sidewall nitride layer.
Preferably, the thickness of the hard mask insulating layer is 120 nm or more. The value of the highest limit of the thickness of the hard mask insulating layer is the maximum value that allows the layer to be fabricated. Preferably, the height of the sidewall nitride layer in the direction perpendicular to the main surface of the semiconductor substrate is larger than the thickness of the gate electrode in the perpendicular direction by 20 nm or more.
The inventors of the present invention noted the relation between generation of leakage current generated between the gate electrode and the interconnection layer in the structure shown in FIG. 1 of the present invention, and a value d(nm) of the difference between the height of the sidewall nitride layer and thickness of the gate electrode, and examined the relation. The result is shown in FIG. 4. The result shown in FIG. 4 proves that generation of leakage current can be almost eliminated if the value of d is 20 nm or more. In addition, the inventors of the invention noted the relation between the value of d and the thickness a (nm) of the hard mask insulating layer, and examined it. The result is shown in FIG. 3. As shown in FIG. 3, the value of d becomes 20 nm or more when the value of the thickness a is 120 nm or more. Accordingly, by setting the value of the thickness a of the hard mask insulating layer at 120 nm or more, the value of d can be set at 20 nm or more, so that generation of leakage current between the gate electrode and the interconnection layer can be effectively minimized.
A concave portion may be formed at the main surface of the semiconductor substrate in the vicinity of the sidewall nitride layer. Preferably, a part of the interconnection layer fills the inside of the concave portion.
A layer which is changed in quality located at the bottom of the contact hole can be removed by providing the concave portion at the semiconductor substrate. The part of the interconnection layer which fills the inside of the concave portion reduces contact resistance between the interconnection layer and the semiconductor substrate.
The upper portion of the other surface of the gate electrode may be recessed from the side surface of the hard mask insulating layer toward the inside of the gate electrode.
As shown in FIG. 1, the sidewall nitride layer has a shape which tapers in width towards the upper portion (in the direction away from the semiconductor substrate). Therefore, insulation between the upper corner portion of the gate electrode and the interconnection layer is necessary. If the upper portion of the other side surface of the gate electrode located on the side of the interconnection layer is recessed into the gate electrode, a distance between the upper corner portion of the gate electrode and the interconnection layer can be increased. As a result, withstand voltage between the gate electrode and the interconnection layer can be improved.
The semiconductor device may have a memory cell portion and a peripheral circuit portion. In this case, the gate electrode is arranged within the memory cell portion. Within the peripheral circuit portion, another gate electrode having a metal silicide part at its upper portion is formed. On a top surface of the another gate electrode, another hard mask insulating layer is formed. Another thin insulating layer is formed to cover a side surface of the another gate electrode and the another hard mask insulating layer. A pair of another sidewall nitride layers is directly formed on the another thin insulating layer to cover both side surfaces of the another gate electrode. The interlayer insulating layer extends over the another hard mask insulating layer to be in contact with a top surface of the another hard mask insulating layer, and another contact hole which penetrates the interlayer insulating layer, the another hard mask insulating layer and the metal silicide part after and has its bottom surface within the another gate electrode is formed. Another interconnection layer is formed in the another contact hole to be electrically connected to the another gate electrode.
The nitride stopper layer does not cover the top surface of the another hard mask insulating layer located in the peripheral circuit portion. Therefore, using the same mask, the contact hole that reaches the main surface of the semiconductor substrate can be formed in the memory cell portion in the self alignment manner, and another contact hole which penetrates the metal silicide part and has its bottom surface in the gate electrode can be formed in the peripheral circuit portion. As a result, the fabrication process can be simplified and the cost can be reduced.
According to one aspect of a method of fabricating a semiconductor device according to the present invention, steps as described below are provided. A gate electrode is formed on a main surface of a semiconductor substrate. A hard mask insulating layer is provided on a top surface of the gate electrode. A thin insulating layer is formed to cover the gate electrode and the hard mask insulating layer. A nitride stopper layer is directly formed on the thin insulating layer. An interlayer insulating layer is formed to cover the nitride stopper layer. By etching the interlayer insulating layer, the nitride stopper layer, and the thin insulating layer successively, a contact hole formed in the self alignment manner which reaches the main surface of the semiconductor substrate, as well as a sidewall nitride layer formed on a side surface of the gate electrode are provided. An interconnection layer is formed in the contact hole.
According to the one aspect of the method of fabricating a semiconductor device according to the present invention as described above, the nitride stopper layer is directly provided on the thin insulating layer, and SiO2 sidewall spacer 15 is not formed between the thin insulating layer and the nitride stopper layer as in the conventional semiconductor device. Therefore, the plasma is not applied to the main surface of the semiconductor substrate, so that generation of leakage current can be effectively minimized and both occurrences of an to. In addition, an area of an opening at the bottom of the contact hole can be increased compared with the conventional device when the contact hole is formed in the self alignment manner between gate electrodes adjacent to each other. Further, since SiO2 sidewall spacer 15 is not formed, the fabrication process can be simplified to reduce the cost. Insulation between the gate electrode and the interconnection layer can be obtained by the presence of the sidewall nitride layer.
The step of forming the contact hole may include a step of forming a concave portion by isotropically etching the main surface of the exposed semiconductor substrate. Further, the step of forming the interconnection layer may include a step of forming an interconnection layer such that the layer fills the concave portion.
By isotropically etching the main surface of the semiconductor substrate as described above, a layer which is different in quality located at the bottom of the contact hole can be removed, and the concave portion can be formed. Contact resistance between the interconnection layer and the semiconductor substrate can be decreased by filling a part of the interconnection layer in the concave portion.
The step of forming the hard mask insulating layer may include a step of forming a hard mask insulating layer such that it has a thickness of 120 nm or more. The step of forming the sidewall nitride layer may include a step of forming a sidewall nitride layer such that the height of the sidewall nitride layer in the direction perpendicular to the main surface of the semiconductor substrate is larger than the thickness of the gate electrode in the perpendicular direction by 20 nm or more.
By setting the thickness of the hard mask insulating layer at 120 nm or more, the difference between the height of the sidewall nitride layer in the direction perpendicular to the main surface of the semiconductor substrate and that of the gate electrode in the perpendicular direction d can be set at 20 nm or more. Generation of leakage current between the gate electrode and the interconnection layer can be effectively minimized by setting the value of d at 20 nm or more as shown in FIG. 4. As a result, a semiconductor device in which improved withstand voltage between the gate electrode and the interconnection layer is obtained can be provided.
The method of fabricating a semiconductor device described above may include a step of recessing an upper portion of the side surface of the gate electrode into the gate electrode from the side surface of the hard mask insulating layer, by etching the upper portion of the side surface of the gate electrode after the hard mask insulating layer is formed.
A distance between the upper corner portion of the gate electrode and the interconnection layer can be increased by recessing the upper portion of the side surface of the gate electrode into the gate electrode from the side surface of the hard mask insulating layer. The most important issue of the semiconductor device is the withstand voltage between the upper corner portion of the gate electrode and the interconnection layer as described above. Therefore, increase of the distance between the upper corner portion of the gate electrode and the interconnection layer allows a semiconductor device having an improved withstand voltage between the gate electrode and the interconnection layer to be provided.
According to another aspect of the method of fabricating a semiconductor device according to the present invention, the method to comprises for fabricating a semiconductor device having a memory cell portion and a peripheral circuit portion. The fabrication method of a semiconductor device according to this aspect includes the processes described below. A first hard mask insulating layer is formed on a main surface of a semiconductor substrate located in the memory cell portion with a first gate electrode interposed, and a second hard mask insulating layer is formed on a main surface located in the peripheral circuit portion with a second gate electrode interposed. A thin insulating layer is formed to cover the first and second hard mask insulating layers as well as side surfaces of the first and second gate electrodes. A nitride stopper layer is directly provided on the thin insulating layer. A first mask layer is formed to cover the nitride stopper layer located within the memory cell portion. The second hard mask insulating layer is exposed and a pair of sidewall nitride layers that covers the side surface of the second gate electrode is formed by etching the nitride stopper layer using the first mask layer. An interlayer insulating layer is provided to cover the nitride stopper layer and the second hard mask insulating layer. A second mask layer is formed on the interlayer insulating layer. Using the second mask layer, a first contact hole that is formed in self alignment manner and selectively exposes the main surface of the semiconductor substrate is provided by etching the interlayer insulating layer, the nitride stopper layer, and the thin insulating layer located in the memory cell portion successively, and a second contact hole which reaches the second gate electrode is formed by successively etching the interlayer insulating layer and the second hard mask insulating layer located within the peripheral circuit portion. First and the second interconnection layers are respectively formed in the first and second contact holes.
The nitride stopper layer on the second hard mask insulating layer is preliminary removed using the first mask layer. Therefore, using the second mask layer, the first contact hole formed in the self alignment manner can be formed in the memory cell portion and the second contact hole can be provided in the peripheral circuit portion. Since the first and second contact holes can be formed by using the same mask, the fabrication process can be simplified to decrease the fabrication cost.
The second gate electrode may include a metal silicide part at its upper portion. In this case, the steps of forming the first and second contact holes may include a step of forming a concave portion at the main surface of the semiconductor substrate after the main surface is exposed and forming the second contact hole such that the hole penetrates the metal silicide part.
Since the concave portion is formed at the main surface of the semiconductor substrate, the area where the interconnection layer and the semiconductor substrate are in contact with each other can be increased, resulting in reduction of contact resistance therebetween. Further, the second contact hole is formed to penetrate the metal silicide part, so that a portion of the gate electrode other than the metal silicide part and the interconnection layer can be in contact with each other. For example, if the interconnection layer is formed of doped polysilicon, impurities from the interconnection layer are absorbed by the metal silicide part since the metal silicide part of the second gate electrode is in contact with the interconnection layer. As a result, a portion where an impurity concentration is low is generated where the second gate electrode and the interconnection layer are connected to each other, and contact resistance between the second gate electrode and the interconnection layer increases. In particular, if the interconnection layer is in contact with only the metal silicide part, a problem is an increase of the contact resistance. If the interconnection layer is in contact with the portion other than the metal silicide part, generation of the portion where the impurity concentration is low can be limited to achieve reduction of the contact resistance.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.